From seismic monitoring to audio to wireless applications, delta-sigma (DS) analogue-to-digital converters (ADCs) have been widely used due to their relaxed analogue requirements, inherent anti-aliasing filtering and low power consumption. With the widespread use of portable electronic equipment, low-power and low-cost designs become crucially important in many applications. Hence there have been many proposals and novel implementations to improve the with the aim of cost and power-consumption reduction.
The quantizers of such ADCs can be implemented in many ways, but usually operate by comparing an analogue signal to a series of references, and then generating an n-bit digital output in accordance with the comparisons. In certain applications a greater number of bits in the quantizer can be desirable for many reasons.
One possible implementation uses one or more reference ladders (e.g. a chain of series-connected resistors) to generate a series of voltages at the nodes between the resistors, all separated by a reference voltage equal to the voltage drop across the resistor.
In a stable and low-cost industrial design, due to the mismatch between components, the reference ladders may require reference voltages of the order of 50 mV or more, otherwise calibration and trimming may be needed. For a 3-bit output signal, requiring six resistors, such a reference ladder will consume headroom of 300 mV; for a 4-bit output signal, requiring 14 resistors, the reference ladder will consume headroom of 700 mV.
The input signal to be quantized may also add to the total voltage swing of the reference ladder, and thus it is clear that output signals having a resolution of 4-bits or greater will be difficult to achieve in low-voltage applications, due to the excess headroom required by the reference ladders. A solution is needed.